This invention relates to a method of manufacturing a semiconductor apparatus, and more particularly, to a technique of electrically isolating a semiconductor element formed on a semiconductor substrate.
To date, the LOCOS method (Local Oxidation Silicon Method) has been widely known as a technique for electrically isolating a semiconductor element. As seen from FIG. 1A, the LOCOS method comprises the steps of forming acid-resisting layer 3, for example, silicon nitride layer (Si.sub.3 N.sub.4) on a semiconductor silicon substrate with silicon oxide layer 2 interposed there-between, patterning the layer, selectively oxidizing the patterned layer with acid-resisting layer 3 used as a mask as shown in FIG. 1B, and providing thick insulation layer 4 for electrical isolation of a semiconductor element.
However, the above-mentioned LOCOS method has the drawback in that when, as shown in FIG. 1A, an opening is formed in acid-resisting layer 3 to expose silicon oxide layer 2, and semiconductor layer 1 is selectively oxidized with acid-resisting layer 3 used as a mask, then a difference appears, as shown in FIG. 1B, between length a of the opening of acid-resisting layer 3 of FIG. 1A and the length of broadened portion b of semiconductor element-isolating layer 4. Now let it be assumed that acid-resisting layer 3 has a thickness of 2500 .ANG.; silicon oxide layer 2 interposed between semiconductor silicon substrate 1 and acid-resisting layer 3 has a thickness of 1500 .ANG.; semiconductor-isolating insulation layer 4 used at the time of selective oxidation has a thickness of 5000 to 6000 .ANG.. Then a difference between the aforementioned lengths a and b indicates 1.2 to 1.6 microns. When, therefore, it is attempted to provide a thoroughly electrically-insulating layer for electrical isolation of a semiconductor element, by using the LOCOS method, a limitation of about 2.0 microns is imposed on the effective width of the element-isolating insulation layer. Consequently, the LOCOS method has the drawback in that it is unsuited for isolation of a semiconductor element having a width narrower than the above-mentioned width limit.
Further, it has been experimentally confirmed that a definite relationship exists between the width and the thickness of an insulation layer used for the isolation of the semiconductor element; and that if the width of the element-isolating insulation layer is reduced, then its thickness also decreases; and that it is then impossible to realize a sufficient electrical isolation property for a semiconductor element. Now, assume that a semiconductor element-isolating insulation layer finished under the aforementioned conditions has a width of 1.4 microns. If, in this case, the occurrence of crystal defects in the semiconductor is taken into account, the resultant semiconductor element-isolating insulation layer will have a maximum thickness of about 3000 to 3200 .ANG.. It is difficult to produce the insulation layer with a greater thickness than the above-mentioned level.
The thickness of insulation layer 4 for isolating semiconductor elements is defined by the relation between said thickness and the impurity concentration in the conductivity reversion-preventing layer underlying said insulation layer 4. The higher the impurity concentration, the greater the thickness of said insulation layer 4. However, of said conductivity reversion-preventing layer is allowed to contain an underly large amount of impurity, a decline will result in the resistance of a semiconductor element to electric conductivity and its operating speed, thereby determining to property of the semiconductor element.
As mentioned above, the conventional semiconductor apparatus manufacturing method which involves the formation of semiconductor element-isolating insulation layer 4 by the LOCOS process has the drawback in that the opened region of acid-resisting layer 3 and semiconductor element-isolating insulating layer 4 noticeably differ in length; and the semiconductor element-isolating insulation layer 4 fails to be formed with a sufficient thickness in the narrow prescribed semiconductor element-isolating region.